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1 of 28 020998 features 4096 bits of nonvolatile dual-port memory including real time clock/calendar in binary format, programmable interval timer, and programmable power-on cycle counter 1-wire tm interface for microlan communication at 16.3k bits per second 3-wire host interface for high-speed data communications at 2m bits per second unique, factory-lasered and tested 64-bit registration number (8-bit family code + 48- bit serial number + 8-bit crc tester) assures absolute traceability because no two parts are alike memory partitioned into 16 pages of 256-bits for packetizing data 256-bit scratchpad with strict read/write protocols ensures integrity of data transfer programmable alarms can be set to generate interrupts for interval timer, real time clock, and/or cycle counter 16-pin dip, soic and ssop packages operating temperature range from -40c to +85c operating voltage range from 2.8 to 5.5 volts ordering information DS2404 16-pin dip DS2404s 16-pin soic DS2404b 16-pin ssop pin assignment pin description v cc ? 2.8 to 5.5 volts irq ? interrupt output rst ? 3-wire reset input dq ? 3-wire input/output i/o ? 1-wire input/output clk ? 3-wire clock input nc ? no connection gnd ? ground v batb ? battery backup input v bato ? battery operate input 1 hz ? 1 hz output x 1 ,x 2 ? crystal connections description the DS2404 econoram time chip offers a simple solution for storing and retrieving vital data and time information with minimal hardware. the DS2404 contains a unique lasered rom, real-time clock/calendar, interval timer, cycle counter, programmable interrupts and 4096-bits of sram. two separate ports are provided for communication, 1-wire and 3-wire. using the 1-wire port, only one pin is required for communication, and the lasered rom can be read even when the DS2404 is without power. the 3-wire port provides high speed communication using the traditional dallas semiconductor 3-wire interface. with either interface, a strict protocol for accessing the DS2404 ensures data integrity. utilizing backup energy sources, the data is nonvolatile and allows for stand-alone operation. the DS2404 features can be used to create a stopwatch, alarm clock, time and date stamp, logbook, hour meter, calendar, system power cycle timer, expiration timer, and event scheduler. vcc 1 16 vcc irq 2 15 x1 rst 3 14 x2 dq 4 13 gnd i/o 5 12 nc clk 6 11 1hz nc 7 10 vbato gnd 8 9 vbatb 16-pin dip (300 mil) 16-pin soic (300 mil) 16-pin ssop (300 mil) see mechanical drawings section DS2404 econoram time chip www.dalsemi.com
DS2404 2 of 28 020998 detailed pin description pin symbol description 1,16 v cc power input pins for v cc operate mode. 2.8 to 5.5 volts operation. either pin can be used for v cc . only one is required for normal operation. (see v bato pin description and ?power control? section). 2 irq interrupt output pin: open drain. 3 rst reset input pin for 3-wire operation. (see ?parasite power? section.) 4 dq data input/output pin for 3-wire operation. 5 i/o data input/output for 1-wire operation: open drain. (see ?parasite power? section.) 6 clk clock input pin for 3-wire operation. 7,12 nc no connection pins. 8,13 gnd ground pin: either pin can be used for ground. 9 v batb battery backup input pin : battery voltage can be 2.8 to 5.5 volts. (see v bato pin description and ?power control? section.) 10 v bato battery operate input pin for 2.8 to 5.5 volt operation. the v cc & v batb pins must be grounded when this pin is used to power the chip. (see ?power control? section.) 11 1hz 1 hz square wave output: open drain. 14,15 x 1 ,x 2 crystal pins . connections for a standard 32.768 khz quartz crystal, epson part number c-002rx or c-004r (be sure to request 6 pf load capacitance). note: x1 and x2 are very high impedance nodes. it is recommended that they and the crystal be guard-ringed with ground and that high frequency signals be kept away from the crystal area. see figure 18 and application note 58 for details. overview the DS2404 has four main data components: 1) 64-bit lasered rom, 2) 256-bit scratchpad, 3) 4096-bit sram, and 4) timekeeping registers. the timekeeping section utilizes an on-chip oscillator that is connected to an external 32.768 khz crystal. the sram and timekeeping registers reside in one contiguous address space referred to hereafter as memory. all data is read and written least significant bit first. two communication ports are provided, a 1-wire port and a 3-wire port. a port selector determines which of the two ports is being used. the communication ports and the rom are parasite-powered via i/o, rst , or v cc . this allows the rom to be read in the absence of power. the rom data is accessible only through the 1-wire port. the scratchpad and memory are accessible via either port. if the 3-wire port is used, the master provides one of four memory function commands: 1) read memory, 2) read scratchpad, 3 ) write scratchpad, or 4) copy scratchpad. the only way to write memory is to first write the scratchpad and then copy the scratchpad data to memory. (see figure 6.) if the 1-wire port is used, the memory functions will not be available until the rom function protocol has been established. this protocol is described in the rom functions flow chart (figure 9). the master must first provide one of five rom function commands: 1) read rom, 2) match rom, 3) search rom, 4) skip rom or 5) search interrupt. after a rom function sequence has been successfully executed, the memory functions are accessible and the master may then provide any one of the four memory function commands (figure 6.)
DS2404 3 of 28 020998 the ?power control? section provides for two basic power configurations, battery operate mode and v cc operate mode. the battery operate mode utilizes one supply connected to v bato . the v cc operate mode may utilize two supplies; the primary supply connects to v cc and a backup supply connects to v batb . DS2404 block diagram figure 1 communication ports two communication ports are provided, a 1-wire and a 3-wire port. the advantages of using the 1-wire port are as follows: 1) provides access to the 64-bit lasered rom, 2) consists of a single communication signal (i/o), and 3) multiple devices may be connected to the 1-wire bus. the 1-wire bus has a maximum data rate of 16.3k bits/second and requires one 5k w external pullup. the 3-wire port consists of three signals, rst , clk, and dq. rst is an enable input, dq is bidirectional serial data, and the clk input is used to clock in or out the serial data. the advantages of using the 3- wire port are 1) high data transfer rate (2 mhz), 2) simple timing, and 3) no external pullup required. port selection is accomplished on a first-come, first-serve basis. whichever port comes out of reset first will obtain control. for the 3-wire port, this is done by bringing rst high. for the 1-wire port, this is done on the first falling edge of i/o after the reset and presence pulses. (see ?1-wire signaling? section.)
DS2404 4 of 28 020998 more information on how to arbitrate port access is found in section ?device operation modes? later in this document. parasite power the block diagram (figure 1) shows the parasite-powered circuitry. this circuitry ?steals? power whenever the i/o, rst , or v cc pins are high. when using the 1-wire port in battery operate mode, rst and v cc provide no power since they are low. however, i/o will provide sufficient power as long as the specified timing and voltage requirements are met. the advantages of parasite power are two-fold: 1) by parasiting off these pins, battery power is conserved and 2) the rom may be read in absence of normal power. for instance, in battery-operate mode, if the battery fails, the rom may still be read normally. in battery-backed mode, if v cc fails, the port switches in the battery but inhibits communication. the rom may still be read normally over the 1-wire port if rst is low. 64-bit lasered rom each DS2404 contains a unique rom code that is 64 bits long. the first eight bits are a 1-wire family code (DS2404 code is 04h). the next 48 bits are a unique serial number. the last eight bits are a crc of the first 56 bits. (see figure 2.) the 1-wire crc is generated using a polynomial generator consisting of a shift register and xor gates as shown in figure 3. the polynomial is x 8 + x 5 + x 4 + 1. additional information about the dallas 1- wire cyclic redundancy check is available in application note 27, ?understanding and using cyclic redundancy checks with dallas semiconductor i button products?. the shift register bits are initialized to zero. then starting with the least significant bit of the family code, one bit at a time is shifted in. after the 8th bit of the family code has been entered, then the serial number is entered. after the 48th bit of the serial number has been entered, the shift register contains the crc value. shifting in the eight bits of crc should return the shift register to all zeros. 64-bit lasered rom figure 2 crc serial number DS2404 family code 8-bits 48-bit unque number 04h msb lsb 1-wire crc code figure 3
DS2404 5 of 28 020998 memory map figure 4
DS2404 6 of 28 020998 memory the memory map in figure 4 shows a page (32 bytes) called the scratchpad and 17 pages called memory. pages 0 through 15 each contain 32 bytes which make up the 4096-bit sram. page 16 has only 30 bytes which contain the timekeeping registers. the scratchpad is an additional page of memory that acts as a buffer when writing to memory. data is first written to the scratchpad where it can be read back. after the data has been verified, a copy scratchpad command will transfer the data to memory. this process ensures data integrity when modifying the memory. timekeeping a 32.768 khz crystal oscillator is used as the time base for the timekeeping functions. the oscillator can be turned on or off by an enable bit in the control register. the oscillator must be on for the real time clock, interval timer, cycle counter and 1 hz output to function. the timekeeping functions are double buffered. this feature allows the master to read time or count without the data changing while it is being read. to accomplish this, a snapshot of the counter data is transferred to holding registers which the user accesses. this occurs after the eighth bit of the read memory function command. real-time clock the real-time clock is a 5-byte binary counter. it is incremented 256 times per second. the least significant byte is a count of fractional seconds. the upper four bytes are a count of seconds. the real- time clock can accumulate 136 years of seconds before rolling over. time/date is represented by the number of seconds since a reference point which is determined by the user. for example, 12:00a.m ., january 1, 1970 could be a reference point. interval timer the interval timer is a 5-byte binary counter. when enabled, it is incremented 256 times per second. the least significant byte is a count of fractional seconds. the interval timer can accumulate 136 years of seconds before rolling over. the interval timer has two modes of operation which are selected by the man auto/ bit in the control register. in the auto mode, the interval timer will begin counting after the i/o line has been high for a period of time determined by the dsel bit in the control register. similarly, the interval timer will stop counting after the i/o line has been low for a period of time determined by the dsel bit. in the manual mode, time accumulation is controlled by the start stop/ bit in the control register. note: for auto mode operation, the high level on the i/o pin must be greater than or equal to 70% of v cc or v bato . cycle counter the cycle counter is a 4-byte binary counter. it increments after the falling edge of the i/o line if the appropriate i/o line timing has been met. this timing is selected by the dsel bit in the control register. (see ?status/ control? section). note: for cycle counter operation, the high level on the i/o pin must be greater than or equal to 70% of v cc or v bato .
DS2404 7 of 28 020998 alarm registers the alarm registers for the real-time clock, interval timer, and cycle counter all operate in the same manner. when the value of a given counter equals the value in its associated alarm register, the appropriate flag bit is set in the status register. if the corresponding interrupt enable bit(s) in the status register is set, an interrupt is generated. if a counter and its associated alarm register are write protected when an alarm occurs, access to the device becomes limited. (see ?status/control?, ?interrupts?, and the ?programmable expiration? sections.) status/control registers the status and control registers are the first two bytes of page 16 (see ?memory map?, figure 4). status register 7 6 5 4 3 2 1 0 x x cce ite rte ccf itf rtf 0200h 0 rtf real-time clock alarm flag 1 itf interval timer alarm flag 2 ccf cycle counter alarm flag when a given alarm occurs, the corresponding alarm flag is set to a logic 1. the alarm flag(s) is cleared by reading the status register. 3 rte real-time interrupt enable 4 ite interval timer interrupt enable 5 cce cycle counter interrupt enable writing any of the interrupt enable bits to a logic 0 will allow an interrupt condition to be generated when its corresponding alarm flag is set (see ?interrupts? section). control register 7 6 5 4 3 2 1 0 dsel start stop man. auto osc ro wpc wpi wpr 0201h 0 wpr write protect real-time clock/alarm registers 1 wpi write protect interval timer/alarm registers 2 wpc write protect cycle counter/alarm registers don?t care bits read only
DS2404 8 of 28 020998 setting a write protect bit to a logic 1 will permanently write protect the corresponding counter and alarm registers, all write protect bits, and additional bits in the control register. the write protect bits can not be written in a normal manner (see ?write protect/programmable expiration? section). 3 ro read only if a programmable expiration occurs and the read only bit is set to a logic 1, then the DS2404 becomes read only. if a programmable expiration occurs and the read only bit is a logic 0, then only the 64-bit lasered rom can be accessed (see ?write protect/programmable expiration? section). 4 osc oscillator enable this bit controls the crystal oscillator. when set to a logic 1, the oscillator will start operation. when the oscillator bit is a logic 0, the oscillator will stop. 5 auto/ man automatic/ manual mode when this bit is set to a logic 1, the interval timer is in automatic mode. in this mode, the interval timer is enabled by the i/o line. when this bit is set to a logic 0, the interval timer is in manual mode. in this mode the interval timer is enabled by the stop/ start bit. 6 stop/ start stop/ start (in manual mode) if the interval timer is in manual mode, the interval timer will start counting when this bit is set to a logic 0 and will stop counting when set to a logic 1. if the interval timer is in automatic mode, this bit has no effect. 7 dsel delay select bit this bit selects the delay that it takes for the cycle counter and the interval timer (in auto mode) to see a transition on the i/o line. when this bit is set to a logic 1, the delay time is 123 + 2 ms. this delay allows communication on the i/o line without starting or stopping the interval timer and without incrementing the cycle counter. when this bit is set to a logic 0, the delay time is 3.5 0.5 ms. memory function commands the ?memory function flow chart? (figure 6) describes the protocols necessary for accessing the memory. two examples follow the flowchart. three address registers are provided as shown in figure 5. the first two registers represent a 16-bit target address (ta1, ta2). the third register is the ending offset/data status byte (e/s). the target address points to a unique byte location in memory. the first five bits of the target address (t4 :t0) represent the byte offset within a page. this byte offset points to one of 32 possible byte locations within a given page. for instance, 00000b points to the first byte of a page where as 11111b would point to the last byte of a page.
DS2404 9 of 28 020998 the third register (e/s) is a read only register. the first five bits (e4: e0) of this register are called the ending offset. the ending offset is a byte offset within a page. bit 5 (pf) is the partial byte flag. bit 6 (of) is the overflow flag. bit 7 (aa) is the authorization accepted flag. address registers figure 5 7 6 5 4 3 2 1 0 target address (ta1) t7 t6 t5 t4 t3 t2 t1 t0 target address (ta2) t15 t14 t13 t12 t11 t10 t9 t8 ending address with data status (e/s) (read only) aa of pf e4 e3 e2 e1 e0 write scratchpad command [0fh] after issuing the write scratchpad command, the user must first provide the 2?byte target address, followed by the data to be written to the scratchpad. the data will be written to the scratchpad starting at the byte offset (t4 :t0). the ending offset (e4: e0) will be the byte offset at which the host stops writing data. the maximum ending offset is 11111b (31d). if the host attempts to write data past this maximum offset, the overflow flag (of) will be set and the remaining data will be ignored. if the user writes an incomplete byte and an overflow has not occurred, the partial byte flag (pf) will be set. read scratchpad command [ aah] this command may be used to verify scratchpad data and target address. after issuing the read scratchpad command, the user may begin reading. the first two bytes will be the target address. the next byte will be the ending offset/data status byte (e/s) followed by the scratchpad data beginning at the byte offset (t4: t0). the user may read data until the end of the scratchpad after which the data read will be all logic 1?s. copy scratchpad [55h] this command is used to copy data from the scratchpad to memory. after issuing the copy scratchpad command, the user must provide a 3-byte authorization pattern. this pattern must exactly match the data contained in the three address registers (ta1, ta2, e/s, in that order). if the pattern matches, the aa (authorization accepted) flag will be set and the copy will begin. at this point, the part will go into a t x mode, transmitting a logic 1 to indicate the copy is in progress. a logic 0 will be transmitted after the data has been copied. any attempt to reset the part will be ignored while the copy is in progress. copy typically takes 30 m s. the data to be copied is determined by the three address registers. the scratchpad data from the beginning offset through the ending offset, will be copied to memory, starting at the target address. anywhere from 1 to 32 bytes may be copied to memory with this command. whole bytes are copied even if only partially written. the aa flag will be cleared only by executing a write scratchpad command.
DS2404 10 of 28 020998 memory function flow chart figure 6
DS2404 11 of 28 020998 read memory [f0h] the read memory command may be used to read the entire memory. after issuing the command, the user must provide the 2-byte target address. after the two bytes, the user reads data beginning from the target address and may continue until the end of memory, at which point logic 1?s will be read. it is important to realize that the target address registers will contain the address provided. the ending offset/data status byte is unaffected. the hardware of the DS2404 provides a means to accomplish error-free writing to the memory section. to safeguard reading data in the 1-wire environment and to simultaneously speed up data transfers, it is recommended to packetize data into data packets of the size of one memory page each. such a packet would typically store a 16-bit crc with each page of data to ensure rapid, error-free data transfers that eliminate having to read a page multiple times to determine if the received data is correct or not. (see the book of ds19xx i button standards, chapter 7 for the recommended file structure to be used with the 1- wire environment.) memory function examples example 1: write one page of data to page 15 read page 15 (3-wire port) master mode data(lsb first) comments tx reset master pulses rst low tx 0fh issue ?write scratchpad? command tx e0h ta1, beginning offset=0 tx 01h ta2, address=01e0h tx <32 data bytes> write 1 page of data to scratchpad tx reset master pulses rst low tx aah issue ?read scratchpad? command rx e0h read ta1, beginning offset=0 rx 01h read ta2, address=01e0h rx 1fh read e/s, ending offset=31d, flags=0 rx <32 data bytes> read scratchpad data and verify tx reset master pulses rst low tx 55h issue ?copy scratchpad? command tx e0h tx 01h tx 1fh ta1 ta2 authorization code e/s rx wait until dq=0 (~30 m s typical) tx reset master pulses rst low tx f0h issue ?read memory? command tx e0h ta1, beginning offset=0 tx 01h ta2, address=01e0h rx <32 data bytes> read memory page 15 and verify tx reset master pulses rst low, done note: the rom function commands do not apply to the 3-wire port. after rst is at a high level, the device expects to receive a memory function command.
DS2404 12 of 28 020998 example 2: write two data bytes to memory locations 0026h and 0027h (the seventh and eighth byte of page 1). read entire memory (1-wire port). master mode data(lsb first) comments tx reset reset pulse (480?960 m s) rx presence presence pulse tx cch issue ?skip rom? command tx 0fh issue ?write scratchpad? command tx 26h ta1, beginning offset=6 tx 00h ta2, address=0026h tx <2 data bytes> write 2 bytes of data to scratchpad tx reset reset pulse rx presence presence pulse tx cch issue ?skip rom? command tx aah issue ?read scratchpad? command rx 26h read ta1, beginning offset=6 rx 00h read ta2, address=0026h rx 07h read e/s, ending offset=7, flags=0 rx <2 data bytes> read scratchpad data and verify tx reset reset pulse rx presence presence pulse tx cch issue ?skip rom? command tx 55h issue ?copy scratchpad? command tx 26h tx 00h tx 07h ta1 ta2 authorization code e/s tx reset reset pulse rx presence presence pulse tx cch issue ?skip rom? command tx f0h issue ?read memory? command tx 00h ta1, beginning offset=0 tx 00h ta2, address=0000h rx <542 bytes> read entire memory tx reset reset pulse rx presence presence pulse, done write protect/programmable expiration the write protect bits (wpr, wpi, wpc) provide a means of write protecting the timekeeping data and limiting access to the DS2404 when an alarm occurs (programmable expiration). the write protect bits may not be written by performing a single copy scratchpad command. instead, to write these bits, the copy scratchpad command must be performed three times. please note that the aa bit will be set, as expected, after the first copy command is successfully executed. therefore, the authorization pattern for the second and third copy command should have this bit set. the read scratchpad command may be used to verify the authorization pattern.
DS2404 13 of 28 020998 the write protect bits, once set, permanently write protects their corresponding counter and alarm registers, all write protect bits, and certain control register bits as shown in figure 7. the time/count registers will continue to count if the oscillator is enabled. if the user wishes to set more than one write protect bit, the user must set them at the same time. once a write protect bit is set it cannot be undone, and the remaining write protect bits, if not set, cannot be set. the programmable expiration takes place when one or more write protect bits have been set and a corresponding alarm occurs. if the ro (read only) bit is set, only the read scratchpad and read memory function commands are available. if the ro bit is a logic ?0?, no memory function commands are available. the rom functions are always available. write protect chart figure 7 write protect bit set: wpr wpi wpc data protected from user modification: real time clock real time alarm wpr wpi wpc ro osc * interval timer interval time alarm wpr wpi wpc ro osc * stop/ start ** auto/ man cycle counter cycle counter alarm wpr wpi wpc ro osc * dsel * becomes write ?1? only, i.e., once written to a logic ?1?, may not be written back to a logic ?0?. ** forced to a logic ?0?. 1-wire bus system the 1-wire bus is a system which has a single bus master and one or more slaves. in most instances the DS2404 behaves as a slave. the exception is when the DS2404 generates an interrupt due to a timekeeping alarm. the discussion of this bus system is broken down into three topics: hardware configuration, transaction sequence, and 1-wire signaling (signal types and timing). hardware configuration the 1-wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. to facilitate this, each device attached to the 1-wire bus must have open drain or 3-state outputs. the 1-wire port of the DS2404 (i/o pin 5) is open drain with an internal circuit equivalent to that shown in figure 8. a multidrop bus consists of a 1-wire bus with multiple slaves attached. the 1-wire bus has a maximum data rate of 16.3k bits per second and requires a pullup resistor of approximately 5k w . the idle state for the 1-wire bus is high. if for any reason a transaction needs to be suspended, the bus must be left in the idle state if the transaction is to resume. if this does not occur and the bus is left low for more than 120 m s, one or more of the devices on the bus may be reset.
DS2404 14 of 28 020998 hardware configuration figure 8 transaction sequence the protocol for accessing the DS2404 via the 1-wire port is as follows: initialization rom function command memory function command transaction/data initialization all transactions on the 1-wire bus begin with an initialization sequence. the initialization sequence consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s). the presence pulse lets the bus master know that the DS2404 is on the bus and is ready to operate. for more details, see the ?1-wire signaling? section. rom function commands once the bus master has detected a presence, it can issue one of the five rom function commands. all rom function commands are eight bits long. a list of these commands follows (refer to flowchart in figure 9): read rom [33h] this command allows the bus master to read the DS2404?s 8-bit family code, unique 48-bit serial number, and 8-bit crc. this command can only be used if there is a single DS2404 on the bus. if more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wired-and result). the resultant family code and 48-bit serial number will usually result in a mismatch of the crc. match rom [55h] the match rom command, followed by a 64-bit rom sequence, allows the bus master to address a specific DS2404 on a multidrop bus. only the DS2404 that exactly matches the 64-bit rom sequence will respond to the following memory function command. all slaves that do not match the 64-bit rom sequence will wait for a reset pulse. this command can be used with a single or multiple devices on the bus.
DS2404 15 of 28 020998 skip rom [ cch] this command can save time in a single drop bus system by allowing the bus master to access the memory functions without providing the 64-bit rom code. if more than one slave is present on the bus and a read command is issued following the skip rom command, data collision will occur on the bus as multiple slaves transmit simultaneously (open drain pulldowns will produce a wired-and result). search rom [f0h] when a system is initially brought up, the bus master might not know the number of devices on the 1- wire bus or their 64-bit rom codes. the search rom command allows the bus master to use a process of elimination to identify the 64-bit rom codes of all slave devices on the bus. the search rom process is the repetition of a simple 3-step routine: read a bit, read the complement of the bit, then write the desired value of that bit. the bus master performs this simple, 3-step routine on each bit of the rom. after one complete pass, the bus master knows the contents of the rom in one device. the remaining number of devices and their rom codes may be identified by additional passes. see chapter 5 of the book of ds19xx i button standards for a comprehensive discussion of a search rom, including an actual example. search interrupt [ ech] this rom command works exactly as the normal rom search, but it will identify only devices with interrupts that have not yet been acknowledged.
DS2404 16 of 28 020998 rom functions flow chart (1-wire port only) figure 9 (see figure 8)
DS2404 17 of 28 020998 1-wire signaling the DS2404 requires strict protocols to ensure data integrity. the protocol consists of five types of signaling on one line: reset sequence with reset pulse and presence pulse, write 0, write 1, read data and interrupt pulse. all these signals except presence pulse and interrupt pulse are initiated by the bus master. the initialization sequence required to begin any communication with the DS2404 is shown in figure 10. a reset pulse followed by a presence pulse indicates the DS2404 is ready to send or receive data given the correct rom command and memory function command. the bus master transmits ( t x ) a reset pulse ( t rstl , minimum of 480 m s). the bus master then releases the line and goes into receive mode ( r x ). the 1-wire bus is pulled to a high state via the pull-up resistor. after detecting the rising edge on the date line, the DS2404 waits ( t pd h , 15-60 m s) and then transmits the presence pulse ( t pdl , 60 - 240 m s). there are special conditions if interrupts are enabled where the bus master must check the state of the 1-wire bus after being in the r x mode for 480 m s. these conditions will be discussed in the ?interrupt? section. read/write time slots the definitions of write and read time slots are illustrated in figure 11. all time slots are initiated by the master driving the data line low. the falling edge of the data line synchronizes the DS2404 to the master by triggering a delay circuit in the DS2404. during write time slots, the delay circuit determines when the DS2404 will sample the data line. for a read data time slot, if a ?0? is to be transmitted, the delay circuit determines how long the DS2404 will hold the data line low overriding the 1 generated by the master. if the data bit is a ?1?, the device will leave the read data time slot unchanged. initialization procedure ?reset and presence pulses? figure 10 480 m s t rstl < * 480 m s t rsth < (includes recovery time) 15 m s t pdh < 60 m s 60 m s t pdl < 240 m s * in order not to mask interrupt signaling by other devices on the 1-wire bus, t rstl + t r should always be less than 960 m s. resistor master DS2404
DS2404 18 of 28 020998 read/write timing diagram figure 11 write-one time slot 60 m s < t slot < 120 m s 1 m s t low1 < 15 m s 1 m s t rec < write-zero time slot 60 m s t low0 < t slot < 120 m s 1 m s t rec < read-data time slot 60 m s t slot < 120 m s 1 m s t lowr < 15 m s 0 t release < 45 m s 1 m s t rec < t rdv = 15 m s t su < 1 m s resistor master DS2404
DS2404 19 of 28 020998 interrupts if the DS2404 detects an alarm condition, it will automatically set the corresponding alarm flag (ccf, itf or rtf) in the status register. if the flag?s corresponding interrupt bit ( rst , ite or rte ) is enabled (logic 0) an interrupt condition begins as the alarm goes off. the DS2404 signals the interrupt condition by pulling the open drain irq output low. the interrupt condition ceases when the alarm flags are cleared (i.e., the interrupt is acknowledged by reading the status register, address 200h) or if the corresponding interrupt enable bit is disabled (set to logic 1). interrupts can also be generated on the 1-wire port. since communication and interrupt signaling share the same pin, one has to distinguish between two types of interrupts: spontaneous interrupts, called type 1, and delayed interrupts, type 2. spontaneous interrupts that have not yet occurred need to be (re- )armed by a reset pulse after all communication on the 1-wire bus has finished. a single falling slope on the 1- wire bus will disarm this type of interrupt. if an alarm condition occurs while the device is disarmed, at first a type 2 interrupt will be produced. spontaneous interrupts are signaled by the DS2404 by pulling the data line low for 960 to 3840 m s as the interrupt condition begins (figure 12). after this long low pulse a presence pulse will follow. if the alarm condition occurs just after the master has sent a reset pulse, i.e., during the high or low time of the presence pulse, the DS2404 will not assert its interrupt pulse until the presence pulse is finished (figure 13). if the DS2404 cannot assert a spontaneous interrupt, either because the data line was not pulled high, communication was in progress, or the interrupt was not armed, it will extend the next reset pulse to a total length of 960 to 3840 m s (delayed interrupt). if the alarm condition occurs during the reset low time of the reset pulse, the DS2404 will immediately assert its interrupt pulse; thus the total low time of the pulse can be extended up to 4800 m s (figure 14). if a DS2404 with a not previously signaled alarm detects a power-on cycle on the 1-wire bus, it will send a presence pulse and wait for the reset pulse sent by the master to extend it and to subsequently issue a presence pulse (figure 15). as long as an interrupt has not been acknowledged by the master, the DS2404 will continue sending interrupt pulses. the interrupt signaling discussed so far is valid for the first opportunity the device has to signal an interrupt. it is not required for the master to acknowledge an interrupt immediately. if an interrupt is not acknowledged, the DS2404 will continue signaling the interrupt with every reset pulse. to do so, DS2404 devices of revision b4 (earlier production parts) will always use the waveform of the type 2 interrupt (figure 14). devices of revision b5 (current production) will either use the waveform of the type 2 interrupt (figure 14) or the waveform of the type 1a interrupt (figure 13). the waveform of the type 2 interrupt will be observed after a communication to a device other than the interrupting one; after successful communication to the interrupting device (without acknowledging the interrupt) the waveform of the type 1a interrupt will be found. the revision code of the DS2404 is appended to the manufacturing date code which is printed on the top of the package right below the part number.
DS2404 20 of 28 020998 type 1 interrupt figure 12 type 1a interrupt (special case) figure 13 type 2 interrupt figure 14 DS2404
DS2404 21 of 28 020998 type 2 interrupt (special case) figure 15 3-wire i/o communications the 3?wire bus is comprised of three signals. these are the rst (reset) signal, the clk (clock) signal, and the dq (data) signal. all data transfers are initiated by driving the rst input high. driving the rst input low terminates communication. (see figures 19 and 20.) a clock cycle is a sequence of a falling edge followed by a rising edge. for data inputs, the data must be valid during the rising edge of a clock cycle. command bits and data bits are input on the rising edge of the clock and data bits are output on the falling edge of the clock. when reading data from the DS2404, the dq pin goes to a high impedance state while the clock is high. taking rst low will terminate any communication and cause the dq pin to go to a high impedance state. power control there are two methods of supplying power to the DS2404, v cc operate mode with battery backup and battery operate mode. if the DS2404 is used in an application where battery backup is not desired, the part must be wired for battery operate mode.
DS2404 22 of 28 020998 v cc operate mode (battery backed) figure 16 shows the necessary connections for operating the DS2404 in v cc operate mode. vcc operate mode figure 16 v cc pin 1 & 16 2.8 to 5.5 volts v batb pin 9 2.8 to 5.5 volts v bato pin 10 must be unconnected to always allow communication through the 1-wire or wire port, the voltage on v cc must be approximately 3- wire port , the voltage on v cc must be approximately 0.2v above the voltage on v batb . otherwise the DS2404 will retain data, but will not allow any access. the v batb pin is normally connected to any standard 3v lithium cell or other energy source. as v cc falls below v batb , the power switching circuit allows v batb to provide energy for maintaining clock functionality and data retention. no communication can take place while v batb is greater than v cc . during power-up, when v cc reaches a value of approximately 0.2v above v batb , the power switching circuit connects v cc and disconnects v batb . if the oscillator is on, no communication can take place until v cc has stayed approximately 0.2v above v bat b for 123 2 ms. during power-down, the falling v cc must pass the range from v batb to 0v in no less than 100 ns for the power switching circuit to function properly.
DS2404 23 of 28 020998 battery operate mode figure 17 shows the necessary connections for operating the DS2404 in battery operate mode. battery operate mode figure 17 v cc pin 1 & 16 ground v batb pin 9 ground v bato pin 10 2.8 to 5.5 volts the v bato pin is normally connected to any standard 3 v lithium cell or other energy source. the battery operate mode also minimizes the power-consumption in applications where battery backup is not required and the v bato lead is directly connected to the system?s 5v supply. note: in battery operate mode, the voltage on dq must never exceed the voltage on v bat o if the 3-wire interface is used. this restriction does not apply to the 1-wire interface. device operation modes with its two ports and two power modes the DS2404 can be operated in several ways. while the maximum voltage on the 1-wire port (i/o) is always 6v, the maximum voltage on the 3-wire port (dq) depends on the power mode and actual operating voltage. a particular port is selected by setting the control lines to a state that makes the other port inactive. see table 1 for details. when using the 3-wire port only and the DS2404 is wired for v cc operate mode (battery backed) the 1- wire i/o pin can be used as counter input. this mode requires that the i/o lead is connected to v cc through a 5k w (typical) resistor. to enable communication through the 3-wire port a reset/presence sequence has to be performed on the 1-wire port after the system has powered up. operation modes and conditions (table 1) port usage battery operate mode v cc operate mode (battery backed) 1-wire only float rst , dq, clk or tie to gnd dq voltage (3-wire) v bato dq voltage (3-wire) v cc +0.3v 3-wire only if unused: float i/o (1-wire) or tie to gnd; if used as counter input: see text dq voltage (3-wire) v bato dq voltage (3-wire) v cc +0.3v 1-wire and 3-wire dual port operation 1-wire port: finish each communication with a reset/presence sequence: when idle: either keep i/o pulled high through a resistor or pull it low; 3-wire port: when idle: keep rst and clk low, keep dq high or low or floating
DS2404 24 of 28 020998 dual port operation the on-chip arbitration logic works on a first- come, first serve principle. assuming that at one time both ports are idle, the one port that becomes active prior to the other one is granted access. activity on the 3- wire port begins as the voltage level on the rst input changes from low to high. the 1-wire port is considered active with the first falling edge detected after the presence pulse. attempting to communicate with the device through the port that temporarily has no access does not affect communication through the other port. if communication on the 1-wire port is initiated while the 3-wire port is active, the device will still respond to the reset pulse, but any subsequently transmitted 1- wire command will be ignored. when reading the rom or memory, for example, the response will always be 1?s, indicating that access was denied. while the 1-wire port is active, the 3-wire data line dq is in tristate mode. the always present resistor of approximately 60 k w pulls dq low. the micro connected to the 3-wire port will fight against this weak pulldown and, depending on its port haracteristics, possibly dominate the logical value on dq. since writing to the memory of the DS2404 requires multiple steps with short periods where both ports are inactive, additional measures are required. to avoid one port overwriting actions initiated by the other port one should do the following: allow the microcontroller operating the 3-wire port to monitor the activity on the 1-wire port. this could be done by means of a retriggerable one-shot, for example. the microcontroller should wait for a break of several milliseconds on the 1-wire port before attempting communication through the 3-wire port. in addition, data should be organized as data packets with a length byte at the beginning and a crc check at the end. whenever one side has finished communication with the DS2404 it should write a token such as a ?null-packet? into the scratchpad. a null-packet consists of three bytes that represent a zero length followed by a valid 16-bit crc. as one port tries to communicate with the device, the first memory function command should be a read scratchpad. communication should only proceed if the null-packet is found. otherwise communication through the other port is not yet finished and one is likely to interfere if one does not immediately release the port for the communication on the other port to resume. for details on recommended data structures please refer to chapters 7 or 10 of the ?book of ds19xx i button standards?.
DS2404 25 of 28 020998 crystal placement on pcb figure 18 3-wire write data timing diagram figure 19 3-wire read data timing diagram figure 20
DS2404 26 of 28 020998 absolute maximum ratings* voltage on data to ground -0.5v to +7.0v operating temperature -40c to +85c storage temperature -55c to +125c soldering temperature 260c for 10 seconds * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended operating conditions (-40 c to +85 c) parameter symbol min typ max units notes logic 1 v ih3 2.2 v cc +0.3 v 1 logic 0 v il3 -0.3 +0.8 v 1 rst logic 1 2.8 5.5 v 1 supply v cc 2.8 5.5 v 1 battery v batb , v bato 2.8 3.0 5.5 v 1,6 dc electrical characteristics (1-wire port) (-40c to +85c; v cc = 5v+ 10%) parameter symbol min typ max units notes logic 1 v ih1 2.2 6.0 v 1,9 logic 0 v il1 -0.3 +0.8 v 1,16 output logic low @ 4ma v ol 0.4 v 1 output logic high v oh v pup v 1,12 input load current i l 5 m a 13 dc electrical characteristics (v cc op. mode) (-40c to +85c; v cc = 5v+ 10%) parameter symbol min typ max units notes output leakage i lo 1 m a 17 output current @ 2.4v on dq i oh 3 ma 18 output current @ 0.4v on dq i ol -3 ma 19 active current i cc1 2 ma 5 standby current i cc2 500 m a 11 dc electrical characteristics (batt. op. mode) (-40c to +85c; v bato = 3.0v) parameter symbol min typ max units notes output leakage i lo 1 m a 17 output current @ 2.4v on dq i oh 1 ma 18 output current @ 0.4v on dq i ol -1 ma 19 i/o operate charge q bato 200 nc 10 battery current (osc on) i bat1 350 na 7 battery current (osc off) i bat2 200 na 7,21
DS2404 27 of 28 020998 capacitance ( t a = 25c) parameter symbol min typ max units notes input capacitance c in 10 pf output capacitance c out 15 pf i/o (1-wire) i in/out 100 800 pf 8 resistances (-40c to +85c) parameter symbol min typ max units notes rst resistance to ground z rst 65 k w dq resistance to ground z dq 65 k w clk resistance to ground z clk 65 k w ac electrical characteristics: 3-wire port (-40c to +85c; v cc = 5v+ 10%) parameter symbol min typ max units notes data to clk setup t dc 35 ns 2 clk to data hold t cdh 40 ns 2 clk to data delay t cdd 100 ns 2,3,4 clk low time t cl 250 ns 2 clk high time t ch 250 ns 2 clk frequency t clk dc 2.0 mhz 2 clk rise and fall t r ,t f 500 ns 2 rst to clk setup t cc 1 m s 2 clk to rst hold t cch 40 ns 2 rst inactive time t cwh 250 ns 2 clk or rst to dq high z t cdz 50 ns 2 ac electrical characteristics: 1-wire port (-40c to +85c; v cc =2.8 to 5.5v) parameter symbol min typ max units notes time slot t slot 60 120 m s write 1 low time t low1 1 15 m s write 0 low time t low0 60 120 m s read low time t lowr 1 15 m s read data valid t rdv exactly 15 m s release time t release 0 15 45 m s read data setup t su 1 m s 15 recovery time t rec 1 m s interrupt t int 960 4800 m s reset time high t rsth 480 m s 14 reset time low t rstl 480 960 m s 20 presence detect high t pdh 15 60 m s presence detect low t pdl 60 240 m s
DS2404 28 of 28 020998 notes: 1. all voltages are referenced to ground. 2. v ih = 2.0v or v il = 0.8v with 10 ns maximum rise and fall time. 3. v dqh = 2.4v and v dql = 0.4v, respectively. 4. load capacitance = 50 pf. 5. measured with outputs open. 6. when battery is applied to v bato input, v cc and v batb must be 0v. 7. v batb , or v bato = 3.0v; all inputs inactive state. 8. capacitance on the i/o pin could be 800 pf when power is first applied. if a 5k w resistor is used to pullup the i/o line to v pup , 5 m s after power has been applied, the parasite capacitance will not affect normal communications. 9. for auto-mode operation of the interval timer, the high level on the i/o pin must be greater than or equal to 70% of v cc or v bato . 10. read and write scratchpad (all 32 bytes) at 3.0v. 11. all other inputs at cmos levels. 12. v pup = external pullup voltage. 13. input load is to ground. 14. an additional reset or communication sequence cannot begin until the reset high time has expired. 15. read data setup time refers to the time the host must pull the i/o line low to read a bit. data is guaranteed to be valid within 1 m s of this falling edge. 16. under certain low voltage conditions v il1max may have to be reduced to as much as 0.5v to always guarantee a presence pulse. 17. applies to 1hz and irq pins only. 18. applies to dq pin only. 19. applies to dq, 1hz and irq pins only. 20. the reset low time ( t rstl ) should be restricted to a maximum of 960 m s, to allow interrupt signaling, otherwise, it could mask or conceal interrupt pulses. 21. when the battery is attached, the oscillator powers up in the off state.

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